View LTC2289CUPPBF_4927826.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc2289 1 2289fa , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. features descriptio u applicatio s u typical applicatio u integrated dual 10-bit adcs sample rate: 80msps single 3v supply (2.7v to 3.4v) low power: 422mw 61.6db snr at 70mhz input 85db sfdr at 70mhz input 110db channel isolation at 100mhz multiplexed or separate data bus flexible input: 1v p-p to 2v p-p range 575mhz full power bandwidth s/h clock duty cycle stabilizer shutdown and nap modes pin compatible family 105msps: ltc2282 (12-bit), ltc2280 (10-bit) 80msps: ltc2294 (12-bit), ltc2289 (10-bit) 65msps: ltc2293 (12-bit), ltc2288 (10-bit) 40msps: ltc2292 (12-bit), ltc2287 (10-bit) 25msps: ltc2291 (12-bit), ltc2286 (10-bit) 64-pin (9mm 9mm) qfn package dual 10-bit, 80msps low noise 3v adc the ltc ? 2289 is a 10-bit 80msps, low noise 3v dual a/d converter designed for digitizing high frequency, wide dynamic range signals. the ltc2289 is perfect for demanding imaging and communications applications with ac performance that includes 61.6db snr and 85db sfdr for signals well beyond the nyquist frequency. dc specs include 0.1lsb inl (typ), 0.1lsb dnl (typ) and 0.6lsb inl, 0.5lsb dnl over temperature. the transition noise is a low 0.08lsb rms . a single 3v supply allows low power operation. a separate output supply allows the outputs to drive 0.5v to 3.6v logic. an optional multiplexer allows both channels to share a digital output bus. a single-ended clk input controls converter operation. an optional clock duty cycle stabilizer allows high perfor- mance at full speed for a wide range of clock duty cycles. snr vs input frequency, ?db, 2v range, 80msps input frequency (mhz) 0 55 snr (dbfs) 56 58 59 60 65 62 50 100 2289 ta02 57 63 64 61 150 200 wireless and wired broadband communication imaging systems spectral analysis portable instrumentation C + input s/h analog input a analog input b clk a clk b 10-bit pipelined adc core clock/duty cycle control output drivers ? ? ? ov dd ognd mux d9a d0a ? ? ? ov dd ognd 2289 ta01 d9b d0b C + output drivers input s/h 10-bit pipelined adc core clock/duty cycle control
ltc2289 2 2289fa parameter conditions min typ max units resolution 10 bits (no missing codes) integral linearity error differential analog input (note 5) C0.6 0.1 0.6 lsb differential differential analog input C0.5 0.1 0.5 lsb linearity error offset error (note 6) C12 212 mv gain error external reference C2.5 0.5 2.5 %fs offset drift 10 v/ c full-scale drift internal reference 30 ppm/ c external reference 5 ppm/ c gain matching external reference 0.3 %fs offset matching 2mv transition noise sense = 1v 0.08 lsb rms the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) co verter characteristics u absolute axi u rati gs w ww u package/order i for atio uu w ov dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................. 4v digital output ground voltage (ognd) ....... C0.3v to 1v analog input voltage (note 3) ..... C0.3v to (v dd + 0.3v) digital input voltage .................... C0.3v to (v dd + 0.3v) digital output voltage ................ C0.3v to (ov dd + 0.3v) power dissipation ............................................ 1500mw operating temperature range ltc2289c ............................................... 0 c to 70 c ltc2289i .............................................C40 c to 85 c storage temperature range ..................C65 c to 125 c order part number qfn part* marking ltc2289up ltc2289cup ltc2289iup consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. top view up package 64-lead (9mm 9mm) plastic qfn t jmax = 125 c, ja = 20 c/w exposed pad (pin 65) is gnd and must be soldered to pcb a ina + 1 a ina C 2 refha 3 refha 4 refla 5 refla 6 v dd 7 clka 8 clkb 9 v dd 10 reflb 11 reflb 12 refhb 13 refhb 14 a inb C 15 a inb + 16 48 da3 47 da2 46 da1 45 da0 44 nc 43 nc 42 nc 41 nc 40 ofb 39 db9 38 db8 37 db7 36 db6 35 db5 34 db4 33 db3 65 64 gnd 63 v dd 62 sensea 61 vcma 60 mode 59 shdna 58 oea 57 ofa 56 da9 55 da8 54 da7 53 da6 52 da5 51 da4 50 ognd 49 ov dd gnd 17 v dd 18 senseb 19 vcmb 20 mux 21 shdnb 22 oeb 23 nc 24 nc 25 nc 26 nc 27 db0 28 db1 29 db2 30 ognd 31 ov dd 32 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
ltc2289 3 2289fa symbol parameter conditions min typ max units snr signal-to-noise ratio 5mhz input 61.6 db 40mhz input 60 61.6 db 70mhz input 61.6 db 140mhz input 61.6 db sfdr spurious free dynamic range 5mhz input 85 db 40mhz input 69 85 db 70mhz input 85 db 140mhz input 80 db sfdr spurious free dynamic range 5mhz input 85 db 40mhz input 74 85 db 70mhz input 85 db 140mhz input 85 db s/(n+d) signal-to-noise plus distortion ratio 5mhz input 61.6 db 40mhz input 60 61.6 db 70mhz input 61.6 db 140mhz input 61.5 db i md intermodulation distortion f in = 40mhz, 41mhz 85 db crosstalk f in = 100mhz e110 db 2nd or 3rd harmonic 4th harmonic or higher the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. a in = e1dbfs. (note 4) dy a ic accuracy u w symbol parameter conditions min typ max units v in analog input range (a in + ea in e ) 2.7v < v dd < 3.4v (note 7) 0.5 to 1v v in,cm analog input common mode (a in + +a in e )/2 differential input (note 7) 1 1.5 1.9 v single ended input (note 7) 0.5 1.5 2 v i in analog input leakage current 0v < a in + , a in e < v dd e1 1 a i sense sensea, senseb input leakage 0v < sensea, senseb < 1v e3 3 a i mode mode input leakage current 0v < mode < v dd e3 3 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay time jitter 0.2 ps rms cmrr analog input common mode rejection ratio 80 db full power bandwidth figure 8 test circuit 575 mhz a alog i put u u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4)
ltc2289 4 2289fa i ter al refere ce characteristics uu u digital i puts a d digital outputs u u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) (note 4) symbol parameter conditions min typ max units logic inputs (clk, oe, shdn, mux) v ih high level input voltage v dd = 3v 2v v il low level input voltage v dd = 3v 0.8 v i in input current v in = 0v to v dd e10 10 a c in input capacitance (note 7) 3 pf logic outputs ov dd = 3v c oz hi-z output capacitance oe = high (note 7) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3v 50 ma v oh high level output voltage i o = e10 a 2.995 v i o = e200 a 2.7 2.99 v v ol low level output voltage i o = 10 a 0.005 v i o = 1.6ma 0.09 0.4 v ov dd = 2.5v v oh high level output voltage i o = e200 a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = e200 a 1.79 v v ol low level output voltage i o = 1.6ma 0.09 v parameter conditions min typ max units v cm output voltage i out = 0 1.475 1.500 1.525 v v cm output tempco 25 ppm/ c v cm line regulation 2.7v < v dd < 3.4v 3 mv/v v cm output resistance e1ma < i out < 1ma 4 ?
ltc2289 5 2289fa power require e ts w u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 8) ti i g characteristics u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3v, f sample = 80mhz, input range = 2v p-p with differential drive, unless otherwise noted. note 5: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from e0.5 lsb when the output code flickers between 00 0000 0000 and 11 1111 1111. note 7: guaranteed by design, not subject to test. note 8: v dd = 3v, f sample = 80mhz, input range = 1v p-p with differential drive. the supply current and power dissipation are the sum total for both channels with both channels active. note 9: recommended operating conditions. symbol parameter conditions min typ max units v dd analog supply voltage (note 9) 2.7 3 3.4 v ov dd output supply voltage (note 9) 0.5 3 3.6 v iv dd supply current both adcs at f s(max) 141 165 ma p diss power dissipation both adcs at f s(max) 422 495 mw p shdn shutdown power (each channel) shdn = h, oe = h, no clk 2 mw p nap nap mode power (each channel) shdn = h, oe = l, no clk 15 mw symbol parameter conditions min typ max units f s sampling frequency (note 9) 1 80 mhz t l clk low time duty cycle stabilizer off 5.9 6.25 500 ns duty cycle stabilizer on (note 7) 5 6.25 500 ns t h clk high time duty cycle stabilizer off 5.9 6.25 500 ns duty cycle stabilizer on (note 7) 5 6.25 500 ns t ap sample-and-hold aperture delay 0 ns t d clk to data delay c l = 5pf (note 7) 1.4 2.7 5.4 ns t md mux to data delay c l = 5pf (note 7) 1.4 2.7 5.4 ns data access time after oe
ltc2289 6 2289fa 8192 point 2-tone fft, f in = 28.2mhz and 26.8mhz, e1db, 2v range typical perfor a ce characteristics uw typical inl, 2v range, 80msps typical dnl, 2v range, 80msps 8192 point fft, f in = 5mhz, e1db, 2v range, 80msps 8192 point fft, f in = 30mhz, e1db, 2v range, 80msps 8192 point fft, f in = 70mhz, e1db, 2v range, 80msps 8192 point fft, f in = 140mhz, e1db, 2v range, 80msps grounded input histogram, 80msps crosstalk vs input frequency input frequency (mhz) 0 e130 crosstalk (db) e125 e120 e115 e110 e105 e100 20 40 60 80 2289 g01 100 code 0 e1.0 inl error (lsb) e0.8 e0.4 e0.2 0 1.0 0.4 256 512 2289 g02 e0.6 0.6 0.8 0.2 768 1024 code 0 e1.0 dnl error (lsb) e0.8 e0.4 e0.2 0 1.0 0.4 256 512 2289 g03 e0.6 0.6 0.8 0.2 768 1024 frequency (mhz) 0 amplitude (db) e60 e40 e20 0 35 2289 g04 e80 e100 e70 e50 e30 e10 e90 e110 e120 5 15 25 10 20 30 40 frequency (mhz) 0 amplitude (db) e60 e40 e20 0 35 2289 g05 e80 e100 e70 e50 e30 e10 e90 e110 e120 5 15 25 10 20 30 40 frequency (mhz) 0 amplitude (db) e60 e40 e20 0 35 2289 g06 e80 e100 e70 e50 e30 e10 e90 e110 e120 5 15 25 10 20 30 40 frequency (mhz) 0 amplitude (db) e60 e40 e20 0 35 2289 g07 e80 e100 e70 e50 e30 e10 e90 e110 e120 5 15 25 10 20 30 40 frequency (mhz) 0 amplitude (db) e60 e40 e20 0 35 2289 g08 e80 e100 e70 e50 e30 e10 e90 e110 e120 5 15 25 10 20 30 40 code 100000 120000 140000 2289 g09 80000 60000 510 511 131072 512 00 40000 20000 0 count
ltc2289 7 2289fa sample rate (msps) 0 0 i ovdd (ma) 2 6 8 10 14 10 50 70 2289 g17 4 12 40 90 100 20 30 60 80 sample rate (msps) 0 95 i vdd (ma) 105 125 135 145 165 10 50 70 2289 g16 115 155 40 90 100 20 30 60 80 2v range 1v range typical perfor a ce characteristics uw snr and sfdr vs sample rate, 2v range, f in = 5mhz, e1db snr and sfdr vs clock duty cycle, 80msps snr vs input level, f in = 70mhz, 2v range, 80msps i ovdd vs sample rate, 5mhz sine wave input, e1db, o vdd = 1.8v i vdd vs sample rate, 5mhz sine wave input, e1db sfdr vs input level, f in = 70mhz, 2v range, 80msps sfdr vs input frequency, e1db, 2v range, 80msps snr vs input frequency, e1db, 2v range, 80msps input frequency (mhz) 0 55 snr (dbfs) 56 58 59 60 65 62 50 100 2289 g10 57 63 64 61 150 200 input frequency (mhz) 0 85 90 100 150 2289 g11 80 75 50 100 200 70 65 95 sfdr (dbfs) sample rate (msps) 0 snr and sfdr (dbfs) 80 90 100 80 2289 g12 70 60 50 10 20 30 40 50 60 70 90 100 110 sfdr snr clock duty cycle (%) 30 snr and sfdr (dbfs) 75 80 85 60 2289 g13 70 65 40 50 35 65 45 55 70 60 55 90 sfdr: dcs on snr: dcs on snr: dcs off sfdr: dcs off input level (dbfs) e50 snr (dbc and dbfs) 30 40 50 e20 0 2289 g14 20 10 0 e40 e30 dbfs dbc e10 60 70 80 input level (dbfs) e50 0 sfdr (dbc and dbfs) 10 30 40 50 e30 e10 0 90 2289 g15 20 e40 e20 60 70 dbfs dbc 80
ltc2289 8 2289fa uu u pi fu ctio s a ina + (pin 1): channel a positive differential analog input. a ina e (pin 2): channel a negative differential analog input. refha (pins 3, 4): channel a high reference. short together and bypass to pins 5, 6 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 5, 6 with an additional 2.2 f ceramic chip capacitor and to ground with a 1 f ceramic chip capacitor. refla (pins 5, 6): channel a low reference. short together and bypass to pins 3, 4 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 3, 4 with an additional 2.2 f ceramic chip capacitor and to ground with a 1 f ceramic chip capacitor. v dd (pins 7, 10, 18, 63): analog 3v supply. bypass to gnd with 0.1 f ceramic chip capacitors. clka (pin 8): channel a clock input. the input sample starts on the positive edge. clkb (pin 9): channel b clock input. the input sample starts on the positive edge. reflb (pins 11, 12): channel b low reference. short together and bypass to pins 13, 14 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 13, 14 with an additional 2.2 f ceramic chip ca- pacitor and to ground with a 1 f ceramic chip capacitor. refhb (pins 13, 14): channel b high reference. short together and bypass to pins 11, 12 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 11, 12 with an additional 2.2 f ceramic chip ca- pacitor and to ground with a 1 f ceramic chip capacitor. a inb e (pin 15): channel b negative differential analog input. a inb + (pin 16): channel b positive differential analog input. gnd (pins 17, 64): adc power ground. senseb (pin 19): channel b reference programming pin. connecting senseb to v cmb selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to senseb selects an input range of v senseb . 1v is the largest valid input range. v cmb (pin 20): channel b 1.5v output and input common mode bias. bypass to ground with 2.2 f ceramic chip capacitor. do not connect to v cma . mux (pin 21): digital output multiplexer control. if mux is high, channel a comes out on da0-da9, ofa; channel b comes out on db0-db9, ofb. if mux is low, the output busses are swapped and channel a comes out on db0- db9, ofb; channel b comes out on da0-da9, ofa. to multiplex both channels onto a single output bus, connect mux, clka and clkb together. shdnb (pin 22): channel b shutdown mode selection pin. connecting shdnb to gnd and oeb to gnd results in normal operation with the outputs enabled. connecting shdnb to gnd and oeb to v dd results in normal opera- tion with the outputs at high impedance. connecting shdnb to v dd and oeb to gnd results in nap mode with the outputs at high impedance. connecting shdnb to v dd and oeb to v dd results in sleep mode with the outputs at high impedance. oeb (pin 23): channel b output enable pin. refer to shdnb pin function. nc (pins 24 to 27, 41 to 44): do not connect these pins. db0 e db9 (pins 28 to 30, 33 to 39): channel b digital outputs. db9 is the msb. ognd (pins 31, 50): output driver ground. ov dd (pins 32, 49): positive supply for the output driv- ers. bypass to ground with 0.1 f ceramic chip capacitor. ofb (pin 40): channel b overflow/underflow output. high when an overflow or underflow has occurred. da0 e da9 (pins 45 to 48, 51 to 56): channel a digital outputs. da9 is the msb. ofa (pin 57): channel a overflow/underflow output. high when an overflow or underflow has occurred. oea (pin 58): channel a output enable pin. refer to shdna pin function.
ltc2289 9 2289fa shdna (pin 59): channel a shutdown mode selection pin. connecting shdna to gnd and oea to gnd results in normal operation with the outputs enabled. connecting shdna to gnd and oea to v dd results in normal opera- tion with the outputs at high impedance. connecting shdna to v dd and oea to gnd results in nap mode with the outputs at high impedance. connecting shdna to v dd and oea to v dd results in sleep mode with the outputs at high impedance. mode (pin 60): output format and clock duty cycle stabilizer selection pin. note that mode controls both channels. connecting mode to gnd selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 v dd selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 v dd selects 2?s comple- ment output format and turns the clock duty cycle stabi- uu u pi fu ctio s lizer on. v dd selects 2?s complement output format and turns the clock duty cycle stabilizer off. v cma (pin 61): channel a 1.5v output and input common mode bias. bypass to ground with 2.2 f ceramic chip capacitor. do not connect to v cmb . sensea (pin 62): channel a reference programming pin. connecting sensea to v cma selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sensea selects an input range of v sensea . 1v is the largest valid input range. gnd (exposed pad) (pin 65): adc power ground. the exposed pad on the bottom of the package needs to be soldered to ground. fu n ctio n al block diagra uu w figure 1. functional block diagram (only one channel is shown) shift register and correction diff ref amp ref buf 2.2 f 1 f1 f 0.1 f internal clock signals refh refl clock/duty cycle control range select 1.5v reference first pipelined adc stage fifth pipelined adc stage sixth pipelined adc stage fourth pipelined adc stage second pipelined adc stage refh refl clk oe mode ognd ov dd 2289 f01 input s/h sense v cm a in e a in + 2.2 f third pipelined adc stage output drivers control logic shdn of d9 d0
ltc2289 10 2289fa dual digital output bus timing (only one channel is shown) ti i g diagra s w u w t ap n + 1 n + 2 n + 4 n + 3 n + 5 n analog input t h t d t l n e 4 n e 3 n e 2 n e 1 clk d0-d9, of 2289 td01 n e 5 n multiplexed digital output bus timing t apb b + 1 b + 2 b + 4 b + 3 b analog input b t apa a + 1 a e 5 b e 5 b e 5 a e 5 a e 4 b e 4 b e 4 a e 4 a e 3 b e 3 b e 3 a e 3 a e 2 b e 2 b e 2 a e 2 a e 1 b e 1 a + 2 a + 4 a + 3 a analog input a t h t d t md t l clka = clkb = mux d0a-d9a, ofa 2289 td02 d0b-d9b, ofb
ltc2289 11 2289fa dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log (
ltc2289 12 2289fa applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. the clk input is single-ended. the ltc2289 has two phases of operation, determined by the state of the clk input pin. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue amplifier. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is amplified and output by the residue amplifier. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when clk is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that clk transitions from low to high, the sampled input is held. while clk is high, the held input voltage is buffered by the s/h amplifier which drives the first pipelined adc stage. the first stage acquires the output of the s/h during this high phase of clk. when clk goes back low, the first stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the applicatio s i for atio wu u u third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage adc for final evaluation. each adc stage following the first has additional range to accommodate flash and amplifier offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2289 cmos differential sample-and-hold. the analog inputs are connected to the sampling capacitors (c sample ) through nmos transistors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capaci- tance associated with each input. during the sample phase when clk is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. when clk transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when clk is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as clk transitions from figure 2. equivalent input circuit v dd v dd v dd 15 ? ?
ltc2289 13 2289fa high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. single-ended input for cost sensitive applications, the analog inputs can be driven single-ended. with a single-ended input the har- monic distortion and inl will degrade, but the snr and dnl will remain unchanged. for a single-ended input, a in + should be driven with the input signal and a in e should be connected to 1.5v or v cm . common mode bias for optimal performance the analog inputs should be driven differentially. each input should swing 0.5v for the 2v range or 0.25v for the 1v range, around a common mode voltage of 1.5v. the v cm output pin may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with a 2.2 f or greater capacitor. input drive impedance as with all high performance, high speed adcs, the dynamic performance of the ltc2289 can be influenced by the input drive circuitry, particularly the second and third harmonics. source impedance and reactance can influence sfdr. at the falling edge of clk, the sample- and-hold circuit will connect the 4pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when clk rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may applicatio s i for atio wu uu degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance, it is recommended to have a source impedance of 100 ? ? ? ? ? ?
ltc2289 14 2289fa figure 5 shows a single-ended input circuit. the imped- ance seen by the analog inputs should be matched. this circuit is not recommended if low distortion is required. applicatio s i for atio wu uu figure 6. recommended front end circuit for input frequencies between 70mhz and 170mhz figure 8. recommended front end circuit for input frequencies above 300mhz figure 7. recommended front end circuit for input frequencies between 170mhz and 300mhz 25 ? ? ? ? ? ? ? ? ? ? ? ? ?
ltc2289 15 2289fa applicatio s i for atio wu uu reference operation figure 9 shows the ltc2289 reference circuitry consisting of a 1.5v bandgap reference, a difference amplifier and switching and control circuit. the internal voltage refer- ence can be configured for two pin selectable input ranges of 2v ( 1v differential) or 1v ( 0.5v differential). tying the sense pin to v dd selects the 2v range; tying the sense pin to v cm selects the 1v range. the 1.5v bandgap reference serves two functions: its output provides a dc bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to gener- ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor is required for the 1.5v reference output, v cm . this provides a high frequency low impedance path to ground for internal and external circuitry. the difference amplifier generates the high and low refer- ence for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. each output has two pins. the multiple output pins are needed to reduce package inductance. bypass capacitors must be connected as shown in figure 9. each adc channel has an independent reference with its own bypass capacitors. the two channels can be used with the same or different input ranges. other voltage ranges between the pin selectable ranges can be programmed with two external resistors as shown in figure 10. an external reference can be used by applying its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. if the sense pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1 f ceramic capacitor. for the best channel matching, connect an external reference to sensea and senseb. figure 10. 1.5v range adc figure 9. equivalent reference circuit v cm refh sense tie to v dd for 2v range; tie to v cm for 1v range; range = 2 v sense for 0.5v < v sense < 1v 1.5v refl 2.2 f 2.2 f internal adc high reference buffer 0.1 f 2289 f09 4 ?
ltc2289 16 2289fa clk 5pf-30pf etc1-1t 0.1 f v cm ferrite bead differential clock input 2289 f13 ltc2289 clk 100 ? ? ? ?
ltc2289 17 2289fa have a 50% ( 5%) duty cycle. each half cycle must have at least 5.9ns for the adc internal circuitry to have enough settling time for proper operation. an optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. this circuit uses the rising edge of the clk pin to sample the analog input. the falling edge of clk is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. the mode pin controls both channel a and channel b?the duty cycle stabilizer is either on or off for both channels. the lower limit of the ltc2289 sample rate is determined by droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the specified minimum operating fre- quency for the ltc2289 is 1msps. digital outputs table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit. digital output buffers figure 14 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, iso- lated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 ? ?
ltc2289 18 2289fa offset binary output format. connecting mode to 2/3v dd or v dd selects 2?s complement output format. an external resistor divider can be used to set the 1/3v dd or 2/3v dd logic values. table 2 shows the logic states for the mode pin. applicatio s i for atio wu u u sleep and nap modes the converter may be placed in shutdown or nap modes to conserve power. connecting shdn to gnd results in normal operation. connecting shdn to v dd and oe to v dd results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mw. when exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting shdn to v dd and oe to gnd results in nap mode, which typically dissipates 30mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap modes, all digital outputs are disabled and enter the hi-z state. channels a and b have independent shdn pins (shdna, shdnb). channel a is controlled by shdna and oea, and channel b is controlled by shdnb and oeb. the nap, sleep and output enable modes of the two channels are completely independent, so it is possible to have one channel operat- ing while the other channel is in nap or sleep mode. digital output multiplexer the digital outputs of the ltc2289 can be multiplexed onto a single data bus. the mux pin is a digital input that swaps the two data busses. if mux is high, channel a comes out on da0-da9, ofa; channel b comes out on db0-db9, ofb. if mux is low, the output busses are swapped and chan- nel a comes out on db0-db9, ofb; channel b comes out on da0-da9, ofa. to multiplex both channels onto a single output bus, connect mux, clka and clkb together (see the timing diagram for the multiplexed mode). the mul- tiplexed data is available on either data bus?the unused data bus can be disabled with its oe pin. grounding and bypassing the ltc2289 requires a printed circuit board with a clean, unbroken ground plane. a multilayer board with an inter- nal ground plane is recommended. layout for the printed circuit board should ensure that digital and analog signal table 2. mode pin function clock duty mode pin output format cycle stabilizer 0 offset binary off 1/3v dd offset binary on 2/3v dd 2?s complement on v dd 2?s complement off overflow bit when of outputs a logic high the converter is either overranged or underranged. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example, if the converter is driving a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. ov dd can be powered with any voltage from 500mv up to 3.6v. ognd can be powered with any voltage from gnd up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . output enable the outputs may be disabled with the output enable pin, oe. oe high disables all data outputs including of. the data ac- cess and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed op- eration. the output hi-z state is intended for use during long periods of inactivity. channels a and b have independent output enable pins (oea, oeb).
ltc2289 19 2289fa applicatio s i for atio wu u u lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , refh, and refl pins. bypass capaci- tors must be located as close to the pins as possible. of particular importance is the 0.1 f capacitor between refh and refl. this capacitor should be placed as close to the device as possible (1.5mm or less). a size 0402 ceramic capacitor is recommended. the large 2.2 f ca- pacitor between refh and refl can be somewhat further away. the traces connecting the pins and bypass capaci- tors must be kept short and should be made as wide as possible. the ltc2289 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2289 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the pc board. it is critical that all ground pins are connected to a ground plane of sufficient area. clock sources for undersampling undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. a clock source that degrades snr of a full-scale signal by 1db at 70mhz will degrade snr by 3db at 140mhz, and 4.5db at 190mhz. in cases where absolute clock frequency accuracy is relatively unimportant and only a single adc is required, a 3v canned oscillator from vendors such as saronix or vectron can be placed close to the adc and simply connected directly to the adc. if there is any distance to the adc, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. you must not allow the clock to overshoot the supplies or performance will suffer. do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise. the lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a filter close to the adc may be beneficial. this filter should be close to the adc to both reduce roundtrip reflection times, as well as reduce the susceptibility of the traces between the filter and the adc. if you are sensitive to close-in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. if your clock is also used to drive digital devices such as an fpga, you should locate the oscillator, and any clock fan-out devices close to the adc, and give the routing to the adc precedence. the clock signals to the fpga should have series termination at the source to prevent high frequency noise from the fpga disturbing the substrate of the clock fan-out device. if you use an fpga as a programmable divider, you must re-time the signal using the original oscillator, and the re- timing flip-flop as well as the oscillator should be close to the adc, and powered with a very quiet supply. for cases where there are multiple adcs, or where the clock source originates some distance away, differential clock distribution is advisable. this is advisable both from the perspective of emi, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multi- layer pcbs. the differential pairs must be close together, and dis- tanced from other signals. the differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart.
ltc2289 20 2289fa c21 0.1 f c27 0.1 f v dd v dd v dd v dd v dd v cc v cmb c20 2.2 f c18 1 f c23 1 f c34 0.1 f c31 * c17 0.1 f c14 0.1 f c25 0.1 f c28 2.2 f c35 0.1 f c24 0.1 f c36 4.7 f e3 v dd 3v e5 pwr gnd v dd v cc 2289 ai01 c1 0.1 f r16 33 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
ltc2289 21 2289fa applicatio s i for atio wu u u silkscreen top top side
ltc2289 22 2289fa bottom side inner layer 2 gnd inner layer 3 power applicatio s i for atio wu u u
ltc2289 23 2289fa package descriptio u up package 64-lead plastic qfn (9mm 9mm) (reference ltc dwg # 05-08-1705) 9 .00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation wnjr-5 2. all dimensions are in millimeters 3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 4. exposed pad shall be solder plated 5. shaded area is only a reference for pin 1 location on the top and bottom of package 6. drawing not to scale pin 1 top mark (see note 5) 0.40 0.10 64 63 1 2 bottom view?exposed pad 7.15 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 e 0.05 (up64) qfn 1003 recommended solder pad pitch and dimensions 0.70 0.05 7.15 0.05 (4 sides) 8.10 0.05 9.50 0.05 0.25 0.05 0.50 bsc package outline pin 1 chamfer information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ltc2289 24 2289fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 rd/lt 0106 rev a ? printed in usa related parts part number description comments ltc2220 12-bit, 170msps adc 890mw, 67.5db snr, 9mm 9mm qfn package ltc2221 12-bit, 135msps adc 630mw, 67.5db snr, 9mm 9mm qfn package ltc2222 12-bit, 105msps adc 475mw, 67.9db snr, 7mm 7mm qfn package ltc2223 12-bit, 80msps adc 366mw, 68db snr, 7mm 7mm qfn package ltc2224 12-bit, 135msps adc 630mw, 67.5db snr, 7mm 7mm qfn package ltc2225 12-bit, 10msps adc 60mw, 71.4db snr, 5mm 5mm qfn package ltc2226 12-bit, 25msps adc 75mw, 71.4db snr, 5mm 5mm qfn package ltc2227 12-bit, 40msps adc 120mw, 71.4db snr, 5mm 5mm qfn package ltc2228 12-bit, 65msps adc 205mw, 71.3db snr, 5mm 5mm qfn package ltc2230 10-bit, 170msps adc 890mw, 67.5db snr, 9mm 9mm qfn package ltc2231 10-bit, 135msps adc 630mw, 67.5db snr, 9mm 9mm qfn package ltc2232 10-bit, 105msps adc 475mw, 61.3db snr, 7mm 7mm qfn package ltc2233 10-bit, 80msps adc 366mw, 61.3db snr, 7mm 7mm qfn package ltc2245 14-bit, 10msps adc 60mw, 74.4db snr, 5mm 5mm qfn package ltc2246 14-bit, 25msps adc 75mw, 74.5db snr, 5mm 5mm qfn package ltc2247 14-bit, 40msps adc 120mw, 74.4db snr, 5mm 5mm qfn package ltc2248 14-bit, 65msps adc 205mw, 74.3db snr, 5mm 5mm qfn package ltc2249 14-bit, 80msps adc 222mw, 73db snr, 5mm 5mm qfn package ltc2286 10-bit, dual, 25msps adc 150mw, 61.8db snr, 9mm 9mm qfn package ltc2287 10-bit, dual, 40msps adc 235mw, 61.8db snr, 9mm 9mm qfn package ltc2288 10-bit, dual, 65msps adc 400mw, 61.8db snr, 9mm 9mm qfn package ltc2290 12-bit, dual, 10msps adc 120mw, 71.3db snr, 9mm 9mm qfn package ltc2291 12-bit, dual, 25msps adc 150mw, 74.5db snr, 9mm 9mm qfn package ltc2292 12-bit, dual, 40msps adc 235mw, 74.4db snr, 9mm 9mm qfn package ltc2293 12-bit, dual, 65msps adc 400mw, 74.3db snr, 9mm 9mm qfn package ltc2294 12-bit, dual, 80msps adc 422mw, 70.6db snr, 9mm 9mm qfn package ltc2295 14-bit, dual, 10msps adc 120mw, 74.4db snr, 9mm 9mm qfn package ltc2296 14-bit, dual, 25msps adc 150mw, 74.5db snr, 9mm 9mm qfn package ltc2297 14-bit, dual, 40msps adc 235mw, 74.4db snr, 9mm 9mm qfn package ltc2298 14-bit, dual, 65msps adc 400mw, 74.3db snr, 9mm 9mm qfn package ltc2299 14-bit, dual, 80msps adc 444mw, 73db snr, 9mm 9mm qfn package

▲Up To Search▲

Price & Availability of LTC2289CUPPBF

	To Download LTC2289CUPPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .